Going the custom DSP route
The impetus for the DFB mini IDE and this site was a design I was working on. The advanced requirements were more than the standard digital filter component could provide.
- 8 channel ADC threshold and peak monitoring in real-time
- 4 channel x 24-sample linear regression slope calculation to run in the background on demand
These were too heavy to do on the CPU with the other required task and latency target so I set out to learn DFB assembler.
During this learning cycle I found that while the datasheet covers each technical area in detail it lacks a macro view and is somewhat opaque in the pipelining aspects. As with most datasheets, it takes a long time for all of the information to 'click'.
The learning curve can be steep on DFB assembler due to several factors:
- The assembler simulator provides limited visibility of the state of each subsystem within the DFB
- The pipeline delays are not directly documented. The datasheet indicates:
"The instruction pipelining follows Figure 3 for the DFB processor.
The diagram shows the locations of the pipeline registers so you can determine the instruction pipeline latency."
- Perhaps the pipelining is obvious to a professional DSP engineer, but as a newcomer to the domain I did not find it to be clear
In working my way up the learning curve I found very few resources outside of the datasheet, but these stood out:
- Magnus Lundin has been active on the PSoC forums with DFB advice, and also has a site with well-documented example code.
- Aubrey Kagan posted a nice article on calculating RMS using the DFB.
- Chris Keeser and Dan Sweet at Cypress worked on DFB assembler improvements in 2013 and posted a very informative post here describing the pipeline delays. Look for the attachment "Download UsefulDFB_Info.zip" which contains a lot of information not found elsewhere with respect to the pipeline delays.
- There are also a number of examples in the Cypress developer forum.
The tools to make the tools
In order to achieve my design objectives and maintain a reasonable cognitive load I decided to take a few weeks and build a mini-development environment for the DFB. Some of the benefits include:
- Visual diagram of the pipeline delays - you can see when an instruction is queued, when data is loaded, when the calculations take place, and when the output is put on the datapath
- View of the data values as they move through the datapath
- Visual indication of active datapath as configured by the muxes
- Ability 'scrub' backward and forward through the code cycles
- Full detail of ACU / Data ram and address registers at each cycle
- Jump diagram to allow one to easily check that the ACU is positioned on the proper offset at each entry to a label
- Ability to 'schedule' globals ahead of time at specific cycles, instead of hand entering them
- A value converter to switch values between hex, integer, and DFB q.23 values one at a time or in bulk
The Mini DFB IDE source is available free and open source on github.